1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which comprises a multiplicity of memory cells formed on the same semiconductor substrate, each memory cell having two transfer gate MOS transistors and two driver MOS transistors as its basic constituent elements, and which is so designed that the area required for each memory cell is reduced.
2. Description of the Prior Art
As memory cells for static type random-access memories (hereinafter abbreviated as "SRAM's" arranged using MOS transistors (hereinafter abbreviated as "MOST's"), one type of memory cell consisting of two transfer gate MOST's, two driver MOST's and two load resistances has heretofore been known (see the specification of Japanese Patent Laid-Open No. 117181/1982). FIG. 8 is a circuit diagram of this type of conventional SRAM memory cell. In the figure, the reference numerals 1 to 4 denote n-channel MOST's, the MOST's 1 and 2 serving as transfer gate MOST's, and the MOST's 3 and 4 serving as driver MOST's. The numerals 5 and 6 denote source nodes of the driver MOST's 3 and 4, respectively, which are fixed to a fixed potential (e.g., a ground potential). The numerals 10 and 11 denote data lines, 9 a word line, and 7, 8 load resistances for supplying currents which respectively hold bits of data stored at nodes 81, 82 by supplying currents from a power supply potential point Vcc. The load resistances 7 and 8 are generally formed from high-resistance polycrystalline silicon layers. Data is written down into or read out from this memory cell through the data lines 10 and 11 by raising the potential of the word line 9 from a low level to a high level. A multiplicity of memory cells of the type described above are formed on the same semiconductor substrate to constitute a SRAM.
FIG. 9 shows the layout of a SRAM memory cell which has been developed by the present inventors prior to this application. No high-resistance polycrystalline silicon layer is illustrated in this figure. One memory cell and parts of cells which are adjacent thereto are included in the illustrated layout. The reference numerals 18A and 19A denote gate electrode layers for the driver MOST's 3 and 4, 12 a gate electrode layer for the transfer gate MOST's 1 and 2, and 13 to 16 impurity introduced regions which define data lines, respectively. The numeral 26 denotes an impurity introduced region which defines respective source regions of the driver MOST's 3 and 4, the region 26 also serving as respective source regions of driver MOST's 18B, 19D, 19E, l8E, 18F and 19G of the adjacent cells. The source region 26 is grounded to apply a ground potential to the source of each driver MOST.
It should be noted that, in FIG. 9, impurity introduced regions 21 to 25 and 22' define nodes of the memory cells, and the numerals 27 to 31 denote connecting portions for electrically connecting these nodes and the gate electrode layers of the corresponding driver MOST's.
As is well known, the impurity introduced regions 13 to 16, 21, 22, 22', 23 to 25 and 26 are formed in such a manner that a doping impurity is introduced into predetermined portions of the surface of the semiconductor substrate by ion implantation or diffusion technique using as a mask the gate electrode layers of the transfer gate and driver MOST's or a gate insulator film formed under this electrode layer.
Referring next to FIG. 10, which is a sectional view through a portion of the source region 26 and the gate electrodes 18A and 18B of the arrangement shown in FIG. 9, the reference numeral 55 denotes a semiconductor substrate, 52, 26, 54 impurity introduced regions, 18A, 18B gate electroad layers, 71 an insulator film, 72 another insulator film formed for the purpose of leveling the surface of the semiconductor device, and 113, 114 data lines.